Semiconductor device and method for manufacturing the same

ABSTRACT

There is provided a semiconductor device having a ferroelectric capacitor formed on a semiconductor substrate covered with an insulator film, wherein the ferroelectric capacitor comprises: a bottom electrode formed on the insulator film; a ferroelectric film formed on the bottom electrode; and a top electrode formed on the ferroelectric film. The ferroelectric film has a stacked structure of either of two-layer-ferroelectric film or three-layer-ferroelectric film. The upper ferroelectric film is metallized and prevents hydrogen from diffusing in lower ferroelectric layer. Crystal grains of the stacked ferroelectric films are preferably different.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. patent application Ser. No.10/443,107, filed May 22, 2003, which is a divisional of U.S. patentapplication Ser. No. 09/359,324 filed Jul. 23, 1999, which is based uponand claims the benefit of priority from the prior Japanese PatentApplication Nos. 208999/1998, filed Jul. 24, 1998; 324254/1998, filedNov. 13, 1998; and 345368/1998, filed Dec. 4, 1998, the entire contentsof which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to a semiconductor deviceincluding a ferroelectric capacitor having a thin-film structure and amethod of manufacturing the same.

2. Related Background Art

There is known a non-volatile semiconductor memory device using aferroelectric capacitor (which will be hereinafter referred to as a“ferroelectric memory”). The ferroelectric capacitor is formed bystacking a bottom electrode, a ferroelectric film and a top electrode ona substrate. A typical ferroelectric film is formed of a perovskitecompound, such as lead zirconate titanate (PZT; PbZr_(x)Ti_(1-x)O⁻³)(0<x<1), which has a perovskite type crystal structure. When a PZT filmis used, a platinum (Pt) film is typically used as each of the bottomand top electrodes. The ferroelectric memory is capable of non-volatilestoring data by the spontaneous polarization (remnant polarization) ofthe ferroelectric.

Such a ferroelectric memory is capable of holding data without the needof any batteries and of operating at a high speed, so that it beginsbeing applied to a non-contact card (RF-ID; Radio Frequency-Indication)and so forth. The ferroelectric memory is also exactly expected to besubstituted for the existing SRAM, EEPROM flash memory, DRAM or thelike, and to be applied to a logic mixed memory.

However, in the conventional ferroelectric capacitor using PZT, hydrogencauses the decreases of the amount of spontaneous polarization, so thatthe signal margin in FRAM is decreased resulting in the bit failure ofthe memory, and the decrease of reliability and yield of the wholememory.

It has been reported that the spontaneous polarization of aferroelectric capacitor having a Pt/PZT/Pt structure is degraded byannealing in an atmosphere of H₂ (e.g., J. Appl. Phys. Vol. 82, No. 1,July 1997, pp. 341-344). On the other hand, although a technique forimproving the characteristics of a ferroelectric capacitor by decreasingthe concentration of hydrogen in the ferroelectric capacitor isdisclosed in, e.g., Japanese Patent Laid-Open No. 8-8404(1996), thistechnique is not realistic since there is a strict limit to a process.

In addition, a basic process for manufacturing the above describedferroelectric capacitor having the Pt/PZT/Pt structure comprises thesteps of: sequentially depositing a bottom Pt electrode and a PZT filmon a substrate; carrying out a heat treatment for crystallizing thedeposited PZT film; and forming a top Pt electrode on the PZT film.

It has been also reported that the spontaneous polarization of theferroelectric capacitor having the Pt/PZT/Pt structure is degraded by aheat treatment in an atmosphere of hydrogen. This is caused by the factthat a large amount of oxygen vacancy is introduced into the PZT film bythe reducing power of hydrogen and the catalysis of the Pt electrode.

On the other hand, it has been revealed by the inventor's recent studythat when the PZT film is deposited on the bottom Pt electrode to becrystallized, Pt is diffused into PZT film from the bottom Pt electrodein deep range of the PZT film to form a conductive layer. Because thestate of PZT film is an amorphous state so that the rate of thediffusion reaction thereof is high when the PZT film is deposited.

In particular, if the thickness of the PZT film is intended to bedecreased to 100 nm or less, most of the PZT film becomes the conductivelayer. Therefore, it is difficult to carry out the scaling of thethickness of the ferroelectric film.

FIG. 1 shows an example of the processed shape of a ferroelectriccapacitor on a substrate 71. In order to achieve the scale down and highintegration of a memory, a bottom Pt electrode 72, a PZT film 73 and atop Pt electrode 74 are preferably sequentially etched in substantiallyvertical directions to form a ferroelectric capacitor as shown inFIG. 1. However, if it is intended to obtain such a shape of capacitor,there is a problem in that Pt splashed by etching the bottom Ptelectrode 72 is adhered to the side wall of the PZT film 73 again toform a Pt fence to establish a short-circuit between the top and bottomelectrodes.

Moreover, as shown in FIG. 2, the ferroelectric capacitor is finallycovered with a passivation film 75, and connected to an interconnection76. In this structure, the end portion of the layer between the PZT film73 and the bottom Pt electrode 72 directly contacts the passivation film75. Therefore, when hydrogen annealing is carried out, hydrogen passingthrough the passivation film 75 penetrates into the layer between thePZT film 73 and the bottom Pt electrode 72 to cause degradation, such asthe decrease of the amount of polarization and the peeling of films,with age.

It has been known that the characteristics of the ferroelectriccapacitor are degraded by hydrogen during a process for manufacturing anSi-LSL, specifically that the amount of polarization thereof isdecreased by hydrogen during the process. In addition, it has beenproposed that a TiO₂ film, an Al₂O₃ film or the like can be effectivelyused as a protective film for protecting the ferroelectric capacitoragainst such penetrating hydrogen (e.g., see IEDM 97-609-612, IEDM97-617-620). However, in the shape that the layer between the PZT film73 and the bottom Pt electrode 72 is continued from the surface of thebottom Pt electrode 72 extending to the outside of the PZT film 73 asshown in FIG. 2, even if the hydrogen protecting film is provided, it isdifficult to interrupt the reducing element, such as hydrogen, whichpenetrates into the layer between the PZT film 73 and the bottom Ptelectrode 72 along the surface of the bottom Pt electrode 72, so that itis not possible to surely prevent the degradation in characteristics.

SUMMARY OF THE INVENTION

It is therefore a primary object of the present invention to eliminatethe aforementioned problems and to provide a semiconductor device havinga ferroelectric capacitor having a small degradation in characteristics,and a method for manufacturing the same.

In a semiconductor integrated circuit according to one aspect of thepresent invention, the dielectric film of a capacitor has a two-layerstructure, which comprises a first metal oxide, for example,BSTO(Ba_(1-x)Sr_(x)TiO₃), dielectric film on the side of a bottomelectrode, and a second metal oxide dielectric film. The first metaloxide film is crystallized after it is deposited on the bottomelectrode. If the dielectric film has such a stacked dielectric filmstructure, the constituent element of the bottom electrode is diffusedin the first metal oxide film at the step of crystallizing the firstmetal oxide dielectric film, and the first metal oxide dielectric filmis crystallized so as to contain the constituent element of the bottomelectrode. Then, when the first metal oxide dielectric film iscrystallized, the constituent element of the bottom electrodeincorporated into the first metal oxide dielectric film can hardly moveso that the constituent element of the bottom electrode is hardlydiffused even at the step of crystallizing the second metal oxidedielectric film deposited on the first metal oxide dielectric film. Inaddition, if the second metal oxide dielectric film is crystallizedbefore the top electrode is deposited, the constituent element of thetop electrode is not diffused in the second metal oxide dielectric film.Therefore, in the case of a ferroelectric capacitor having first andsecond metal oxide films of ferroelectric films, the second metal oxidefilm has a good ferroelectric characteristic having no leak, so that itis possible to obtain a ferroelectric capacitor having a largespontaneous polarization. In addition, since the constituent element ofthe bottom electrode Is not diffused in the second metal oxidedielectric film, it is possible to easily decrease the thickness of thesecond metal oxide film.

Even in the case of a high-dielectric capacitor wherein each of thefirst and second metal oxide films is a high-dielectric film, it ispossible to obtain an excellent capacitor characteristic having a smallleak for the same reason, so that it is possible to decrease thethickness of the high-dielectric film.

It is to be noted that the first and second metal oxide dielectric filmsare interpreted as ferroelectric materials throughout the specification.

In a semiconductor integrated circuit according to another aspect of thepresent invention, in addition to the first and second metal oxidedielectric films described above, a third metal oxide dielectric film isprovided between the above described second metal oxide dielectric filmand the top electrode. In this case, if the third metal oxide dielectricfilm is crystallized after the top electrode is deposited thereon, thethird metal oxide dielectric film is crystallized so as to contain theconstituent element of the top electrode similar to the first metaloxide dielectric film. Therefore, the third metal oxide dielectric filmserves as a metallic layer against the reducing power due to hydrogen orthe like from the top of the second metal oxide dielectric film. Thus,it is possible to more effectively inhibit the characteristics of theferroelectric capacitor from being degraded by the reducing gas.

It is a further object of the present invention to provide asemiconductor device having a ferroelectric capacitor which caneffectively inhibit the damage to the layer between a ferroelectric filmand a bottom electrode, and the peeling of films and which can reducethe degradation in remnant polarization, and a method for manufacturingthe same.

In the ferroelectric capacitor according to the present invention,although the bottom electrode is patterned so as to extend to theoutside of the ferroelectric film, a part of the surface portion of thebottom electrode is removed by over etching when the ferroelectric filmis patterned, so that the level of the surface of the extending portionof the bottom electrode is lower than that of the layer between theferroelectric film and the bottom electrode. Moreover, the protectivefilm against hydrogen gas and a halogen gas is formed so as to cover aregion extending from the surface of the bottom electrode to the sidesof the ferroelectric film and top electrode. Thus, it is possible toeffectively inhibit the reducing element from penetrating into the layerbetween the ferroelectric film and the bottom electrode, so that it ispossible to obtain a reliable ferroelectric capacitor, the remnantpolarization of which does not decrease, which will result inimprovement of electrical property for FRAMS, and decrease of leak ofcharges and improvement in adaptability for scaling for DRAM

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be understood more fully from the detaileddescription given herebelow and from the accompanying drawings of thepreferred embodiments of the invention. However, the drawings are notintended to imply limitation of the invention to a specific embodiment,but are for explanation and understanding only.

In the attached drawings:

FIG. 1 is a sectional view showing an example of a structure of aconventional capacitor;

FIG. 2 is a sectional view showing the integrated structure of aconventional ferroelectric capacitor;

FIGS. 3A-3F are sectional views showing steps of forming a bottomelectrode of a preferred embodiment of a ferroelectric capacitoraccording to the present invention, wherein FIG. 3A shows a step offorming a bottom electrode, FIG. 3B shows a step of depositing a firstPZT film, FIG. 3C shows a step of crystallizing the first PZT film, FIG.3D shows a step of depositing a second PZT film, FIG. 3E shows a step offorming a top electrode and FIG. 3F shows a step of crystallizing thesecond PZT film, respectively;

FIG. 4A is a sectional view showing an example of the preferredembodiment of a ferroelectric capacitor according to the presentinvention, which is applied to a ferroelectric memory;

FIG. 4B is a sectional view showing a step of patterning the capacitorin the example of FIG. 4A;

FIG. 4C is a sectional view showing the structure of the capacitor inthe example of FIG. 4A after the capacitor is integrated;

FIG. 5 is a schematic diagram showing the crystal structure of thepreferred embodiment of a ferroelectric capacitor according to thepresent invention;

FIG. 6 is a graph showing the results of the SIMS analysis of thepreferred embodiment of a ferroelectric capacitor according to thepresent invention;

FIG. 7 is a graph showing the results of the SIMS analysis of aconventional ferroelectric capacitor; FIG. 8 is a schematic diagramshowing the structure of the conventional ferroelectric capacitor;

FIG. 9 is a graph showing the P-V characteristic of the preferredembodiment of a ferroelectric capacitor according to the presentinvention;

FIG. 10 is a graph showing the P-V characteristic of the conventionalferroelectric capacitor;

FIG. 11 is a sectional view showing the structure of a second preferredembodiment of a ferroelectric capacitor according to the presentinvention;

FIG. 12 is a graph showing the correlation between hydrogenconcentration and spontaneous polarization of the conventionalferroelectric capacitor;

FIG. 13A is a sectional view showing the structure of the thirdpreferred embodiment of a ferroelectric capacitor according to thepresent invention;

FIG. 13B is a sectional view showing a variation of the structure shownin FIG. 13A, which does not have a protective film;

FIGS. 14A through 14C are sectional views showing a process formanufacturing the first preferred embodiment of a ferroelectriccapacitor according to the present invention;

FIG. 15 is a sectional view showing a memory cell structure in the firstpreferred embodiment;

FIG. 16 is a graph showing the polarization characteristic of the firstpreferred embodiment of a ferroelectric capacitor according to thepresent invention, in comparison with that of the conventionalferroelectric capacitor;

FIG. 17 is a graph showing the results of the SIMS analysis of the firstpreferred embodiment of a ferroelectric capacitor according to thepresent invention;

FIG. 18 is a graph showing the results of the SIMS analysis of theconventional ferroelectric capacitor;

FIG. 19A is a sectional view showing the structure of the fourthpreferred embodiment of a ferroelectric capacitor according to thepresent invention;

FIG. 19B is a sectional view showing a variation of the structure shownin FIG. 19A, which does not have a protective film;

FIGS. 20A through 20C are sectional views showing a process formanufacturing the fourth preferred embodiment of a ferroelectriccapacitor according to the present invention;

FIG. 21 is a graph showing the results of the SIMS analysis of thesecond preferred embodiment of a ferroelectric capacitor according tothe present invention:

FIG. 22 is a sectional view showing the structure of the fifth preferredembodiment of a high-dielectric capacitor according to the presentinvention:

FIG. 23 is a sectional view showing the structure of the sixth preferredembodiment of a high-dielectric capacitor according to the presentinvention;

FIG. 24 is a sectional view showing a seventh preferred embodiment of aferroelectric capacitor according to the present invention;

FIGS. 25A through 25D are sectional views showing a process formanufacturing the ferroelectric capacitor of FIG. 24;

FIG. 26 is a sectional view showing an eighth preferred embodiment of aferroelectric capacitor according to the present invention;

FIGS. 27A through 27E are sectional views showing a process formanufacturing the ferroelectric capacitor of FIG. 26;

FIGS. 28A through 28D are sectional views showing a process formanufacturing a ninth preferred embodiment of a ferroelectric capacitorof an FRAM according to the present invention;

FIG. 28E shows a variation of FIG. 28D;

FIGS. 29A through 29D are sectional views showing variations of a tenthpreferred embodiment of a ferroelectric capacitor according to thepresent invention;

FIGS. 30A and 30B are sectional views showing variations of the eleventhpreferred embodiment of a ferroelectric capacitor according to thepresent invention;

FIGS. 31A through 31G show a process for manufacturing a twelfthpreferred embodiment of a ferroelectric capacitor according to thepresent invention;

FIG. 31H is a sectional view showing a structure corresponding to FIG.31G, in which fences are completely removed;

FIG. 32 is a sectional view showing an embodiment which is a combinationof structures of FIG. 26 and FIG. 11;

FIG. 33 is a sectional view showing an embodiment which is a combinationof structures of FIG. 26 and FIG. 13;

FIG. 34 is a sectional view showing an embodiment which is a combinationof structures of FIG. 26 and FIG. 19;

FIG. 35 is a sectional view showing an embodiment which is a combinationof structures of FIG. 26 and FIG. 23;

FIG. 36 is a sectional view showing an embodiment which is a combinationof structures of FIG. 28D and FIG. 11;

FIG. 37 is a sectional view showing an embodiment which is a combinationof structures of FIG. 28D and FIG. 13;

FIG. 38 is a sectional view showing an embodiment which is a combinationof structures of FIG. 28D and FIG. 19;

FIG. 39 is a sectional view showing an embodiment which is a combinationof structures of FIG. 28D and FIG. 23;

FIG. 40 is a sectional view showing an embodiment which is a combinationof structures of FIG. 29A and FIG. 11;

FIG. 41 is a sectional view showing an embodiment which is a combinationof structures of FIG. 29A and FIG. 13;

FIG. 42 is a sectional view showing an embodiment which is a combinationof structures of FIG. 29A and FIG. 19;

FIG. 43 is a sectional view showing an embodiment which is a combinationof structures of FIG. 29A and FIG. 23;

FIG. 44 is a sectional view showing an embodiment which is a combinationof structures of FIG. 30A and FIG. 11;

FIG. 45 is a sectional view showing an embodiment which is a combinationof structures of FIG. 30A and FIG. 13;

FIG. 46 is a sectional view showing an embodiment which is a combinationof structures of FIG. 30A and FIG. 19;

FIG. 47 is a sectional view showing an embodiment which is a combinationof structures of FIG. 30A and FIG. 23;

FIG. 48 is a sectional view showing an embodiment which is a combinationof structures of FIG. 29A and FIG. 31G;

FIG. 49 is a sectional view showing an embodiment which is a combinationof structures of FIG. 29A and FIG. 31H;

FIG. 50 is a sectional view showing an embodiment which is a variationof the combination of structures of FIG. 29A and FIG. 31G;

FIG. 51 is a sectional view showing an embodiment which is a variationof the combination of structures of FIG. 29A and FIG. 31H; and

FIG. 52 is a sectional view showing an embodiment in which an interlayerinsulator material containing metal oxide is used.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to the accompanying drawings, the preferred embodiments ofthe present invention will be described below.

In the following description, most of the embodiments show only thecapacitor part. It is to be noted that contact plugs, interconnections,MOS transistors, etc. are generally provided as shown in FIG. 15 whichwill be described later, but in other Figures, they are omitted.

FIGS. 3A through 3E show a process for manufacturing a first preferredembodiment of a ferroelectric capacitor on a silicon substrate. In FIG.3A, elements, such as MOS transistors, are formed on a silicon substrate1, and a silicon oxide (SiO₂) film 2 for covering the MOS transistor isformed thereon. On the silicon oxide film 2, an adhesion film 3 a havinga thickness of 20 nm is deposited by a sputtering method, andsubsequently, a Pt film 3 b having a thickness of 20 nm is deposited bya sputtering method to form a bottom electrode 3 of a Pt/adhesionstacked film.

Subsequently, as shown in FIG. 3B, a first PZT film 4 a having athickness of 250 nm serving as a ferroelectric film is deposited on thebottom electrode 3 by the sol-gel method or sputtering method. Then, atthis stage, a heat treatment (RTA) is carried out at 750° C. in anatmosphere of oxygen to crystallize the PZT film 4 a.

At this heat treatment step for crystallization, a diffusion reaction iscaused between the bottom electrode 3 and the PZT film 4 a to form adiffusion reaction layer 5 as shown in FIG. 3C. It has been revealed bythe inventor's analysis that the diffusion reaction layer 5 is aPb—Pt—(Ti—)O layer, and that the reason why the diffusion reaction layer5 is formed is that the state of the PZT film 4 a before the heattreatment is an amorphous state.

Thereafter, as shown in FIG. 3D, a second PZT film 4 b having athickness of about 10 nm is deposited on the crystallized first PZT filmby the sol-gel method or the sputtering method at a low temperature. Atthis stage, the state of the PZT film 4 b is an amorphous state.

Then, as shown in FIG. 3E, a Pt film 6 having a thickness of 100 nm isdeposited on the PZT film 4 b by the sputtering method.

Thereafter, a heat treatment (RTA) is carried out at 750° C. in anatmosphere of oxygen to crystallize the PZT film 4 b. At this heattreatment step for crystallization, a diffusion reaction is causedbetween the top electrode 6 and the PZT film 4 b to form a diffusionreaction layer 7 as shown in FIG. 3F. This diffusion reaction layer 7 isalso a Pb—Pt—(Ti—)O layer in which plutinum is diffused.

The foregoing steps have been described with respect to only theferroelectric capacitor. If the above described process is actuallyapplied to, e.g., a ferroelectric memory having memory cells of the sameone-transistor/one-capacitor structure as that of a DRAM, using a MOStransistor and a ferroelectric capacitor, it is as follows.

As shown in FIG. 4A, an element isolating insulator film 11 ispreviously formed in the silicon substrate 1 by, e.g., the embeddingmethod. Then, a MOS transistor 10 having agate electrode 12 andsource/drain diffusion layers 13, 14 is formed. The substrate, on whichthe MOS transistor 10 has been formed, is covered with a CVD siliconoxide film 2 a serving as an interlayer insulator film. In the siliconoxide film 2 a, a contact conductor 15 connected to one diffusion layer13 is embedded. Then, a bit line 16 connected to the contact conductor15 is formed on the silicon oxide film 2 a. The reason why the contactconductor 15 and the bit line 16 are shown by broken lines is that thecontact conductor 15 and the bit line 16 are formed opposite to acontact conductor 17, which is connected to the other diffusion layer 14of the MOS transistor 10, in a direction perpendicular to the plane ofthe drawing.

On the substrate, on which the bit line 16 has been formed, a siliconoxide film 2 b serving as an interlayer insulator film is deposited.Then, the contact conductor 17 connected to the other diffusion layer 14of the MOS transistor 10 is embedded so as to pass through the siliconoxide films 2 a, 2 b. Then, the bottom electrode 3, the PZT film 4 andthe top electrode 6 are stacked on the silicon oxide film 2 b by thesteps shown in FIGS. 3A through 3F. Thereafter, as shown in FIG. 4B, thestacked film is patterned for each memory cell to form a ferroelectriccapacitor 20.

Thereafter, as shown in FIG. 4C, a CVD silicon oxide film 21 serving asan interlayer insulator film is deposited to form a contact hole to thecapacitor 20 to form a plate electrode 22. Moreover, a CVD silicon oxidefilm 23 serving as an interlayer insulator film is deposited thereon toform an interconnection layer 24. The interconnection layer 24 isprotected by a passivation film (not shown).

The internal composition and characteristics of a ferroelectriccapacitor in this preferred embodiment will be described in detailbelow.

FIG. 5 schematically shows the crystal structure of a ferroelectriccapacitor in this preferred embodiment. The first PZT film 4 a is apolycrystalline of an aggregation of crystal grains 41 which havecrystal-grown in directions of axis <111>. Each of the crystal grains 41is defined by grain boundaries 43 perpendicular to the plane of thebottom electrode. It has been confirmed by analysis using a secondaryion mass spectrometer (SIMS) that the layer 44 between the PZT film 4 aand the bottom Pt electrode 3 b is substantially flat and that aPt—Pb—(Ti—)O reaction layer is formed in the layer 44. This point willbe described later.

The second PZT film 4 b becomes crystal grains 42 which have grown onthe crystallized first PZT film 4 a so as to be substantially matchedwith the crystal grains 41 and which have a smaller mean particlediameter than that of the crystal grains 41. Most of excessive Pb at theheat treatment step of crystallizing the first PZT film 4 a is collectedon the surface of the first PZT film 4 a. Therefore, if the top Ptelectrode 6 a is formed directly on the first PZT film 4 a, most of Pbremains in the boundary of the top Pt electrode 6 a. However, in thispreferred embodiment, after the very thin second PZT film 4 b is stackedon the first PZT film 4 a to deposit the top Pt electrode 6 a in anamorphous state, the second PZT film 4 b is crystallized. As a result,excessive Pb does not remain in the layer between the top Pt electrode 6a and the second PZT film 4 b.

FIGS. 6 and 7 show the results of the SIMS analysis of a ferroelectriccapacitor in this preferred embodiment and a conventional ferroelectriccapacitor. As shown in FIG. 8, the conventional ferroelectric capacitorhas a single PZT film 33 as a ferroelectric film. That Is, thisferroelectric capacitor is produced by forming a bottom electrode 32 ofan adhesion film 32 a and Pt film 32 b on a silicon substrate 30 coveredwith a silicon oxide film 31, forming a PZT film 33 thereon, and then,crystallizing the PZT film 33 to form a top Pt electrode 34.

As can be clearly seen from FIG. 7, in the conventional ferroelectriccapacitor, the distribution of Pb is inclined in the PZT film in athickness direction thereof, and the concentration of Pb in the layerbetween the top electrode and the PZT film is higher than that in thelayer between the bottom electrode and the PZT film The reason for thisis that the PZT film is formed on the Pb rich condition so thatexcessive Pb at the heat treatment step for crystallization is collectedon the surface portion of the PZT film in the form of Pb—O.

On the other hand, in the structure of this preferred embodiment, asshown in FIG. 6, although a small peak of concentration of Pb exists inthe vicinity of the top Pt electrode in the PZT film (in the vicinity ofthe layer between the first PZT film and the second PZT film), theconcentration of Pb in the PZT film is substantially even as a whole, sothat at least the concentrations of Pb in the layers between the top andbottom electrodes and the PZT films are substantially equal to eachother. The reason for this is that the mean particle diameters of thecrystal grains in the first and second PZT films are different from eachother, i.e., a grain boundary substantially parallel to the plane of thebottom electrode is formed in the whole layer between the first PZT filmand the second PZT film, and excessive Pb aggregates in the grainboundary, so that the distribution of Pb in the whole PZT film issubstantially even.

Furthermore, even if the concentration of Pb is slightly high in thelayer between the first and second PZT films, the catalysis of Pt isdifficult to have an influence on the layer, so that a great degradationin characteristics is not caused by the reduction reaction of Pb—O.

The characteristics of the ferroelectric capacitor in this preferredembodiment and the conventional ferroelectric capacitor of FIG. 8 areshown in FIGS. 9 and 10, respectively. Both show initial states (solidlines) and states after a heat treatment (hydrogen treatment) in anatmosphere of H₂, with respect to hysteresis characteristics when avoltage of ±5 V is applied In the conventional structure, thespontaneous polarization of hysteresis after hydrogen treatment was2Pr=9 μC/cm². On the other hand, in the structure of this preferredembodiment, the spontaneous polarization of hysteresis was 2Pr=30μC/cm².

It is considered that the reasons why the degradation of the capacitordue to hydrogen is small in this preferred embodiment are as follows Oneof the reasons is the fact that excessive Pb does not exist in the layerbetween the top Pb electrode and the PZT film. That is, even if hydrogenpenetrates into this layer, oxygen vacancy based on the reductionreaction due to the catalysis of the Pt electrode is not very much. Theother reason is the fact that the diffusion reaction layer of Pb—Pt—Ti—Ois formed in the layer between the top Pt electrode and the PZT film toinhibit the catalysis of Pt.

In order to obtain the above described advantages in this preferredembodiment, the top Pt electrode 6 a must be formed when the state ofthe second PZT film 4 b is in amorphous state. On this condition, thePb—Pt—Ti—O reaction layer 7 is formed. In addition, the effectivethickness of the second PZT film 4 b is preferably 150 nm or less, morepreferably about 100 nm or less. It is enough that the minimum thicknessof the second PZT film 4 b is 1 nm.

FIG. 11 shows the structure of a principal part of a second preferredembodiment of a ferroelectric capacitor according to the presentinvention. In this preferred embodiment unlike the preceding preferredembodiment, very thin Ti films 8 and 9 are formed in the layer betweenthe Pt films 3 b, 6 a of the top and bottom electrodes and the PZT films4 a, 4 b, respectively. These Ti films 8 and 9 serve as nuclei for thecrystal growth of the PZT films 4 a and 4 b, and promote the formationof the diffusion reaction layer of Pb—P—(Ti—)O. The thickness of the Tifilms 8 and 9 may be in the range of about 0.5 nm to about 10 nm. Otherconditions are the same as those in the preceding preferred embodiment.

According to this preferred embodiment, it is possible to obtain abetter crystalline PZT film, and to sufficiently form diffusion reactionlayers in the layers between the PZT films and the Pt films of the topand bottom electrodes to inhibit the aggregation of Pb—O.

As described above, according to the present invention, the structure ofthe capacitor and the method for manufacturing the same are improved sothat the fixed charge due to oxygen vacancy is not produced even ifhydrogen penetrates into the layer between the top Pt electrode and thePZT film. On the other hand, after the inventors analyzed non-defectiveand defective samples of the conventional ferroelectric capacitors shownin FIG. 8, it was revealed that if the concentration of hydrogen wasabout 1×10²⁰/cm³ in the layer between the top Pt electrode and the PZTfilm, then there was a remarkable decrease of spontaneous polarization.

FIG. 12 shows the correlation between the concentration of hydrogen inthe layer between the top Pt electrode and the PZT film, and thespontaneous polarization Pr of the capacitor, which was obtained by theabove-described analysis. From these data, it is found that thespontaneous polarization rapidly decreases if the concentration ofhydrogen exceeds a certain level.

In the case of the ferroelectric memory produced by the LSI processdescribed in FIGS. 4A through 4C, the concentration of hydrogen in theferroelectric capacitor is difficult to be 1×10¹⁹/cm³. Because it is notpossible to prevent hydrogen from penetrating from the interlayerinsulator films 21, 23 on the capacitor 20 shown in FIG. 4C and from amolding material (not shown) formed thereon. Therefore, even in the caseof the conventional ferroelectric capacitor, if the hydrogenconcentration of the capacitor is small in the range of from 1×10¹⁹/cm³to 1×10²⁰ cm³, preferably in the range of from 2×10¹⁹/cm³ to1×10²⁰/cm⁻³, it is possible to obtain good characteristics which do notcause the decrease of spontaneous polarization.

In order to confine the hydrogen concentration of the capacitor withinthe above described range, it is enough that the interlayer insulatorfilms 21 and 22 on the capacitor 20 shown in FIG. 4C has a hydrogenconcentration of 1×10²⁰/cm³ or less. Moreover, the interlayer insulatorfilms 21 and 23 preferably have a hydrogen diffusion coefficient of1×10⁻⁷ cm² or less. In order to decrease the hydrogen diffusioncoefficient of the interlayer insulator film, there is considered amethod for adding N (nitrogen) into the silicon oxide film. From thispoint of view, a material having an evaporated hydrogen amount of 50 ppbor less is preferably selected as the molding material.

Of course, it is effective to set the above described hydrogenconcentration range even in the case of the structure of the capacitorin the above described preferred embodiment.

FIG. 13A shows the structure of a third preferred embodiment of aferroelectric capacitor C1 according to the present invention. Asubstrate 110 is a silicon substrate covered with an insulator film of asilicon oxide film or the like. A Pt electrode 112 serving as a bottomelectrode is formed on the substrate 110 via an adhesion film 111. Onthe Pt electrode 112, a first PZT film 113 and a second PZT film 114 arestacked. On the second PZT film 114, a Pt electrode 115 is formed as atop electrode.

In this preferred embodiment, the ferroelectric capacitor C1 ispatterned as shown in the figure, and covered with a protective film 116against a reducing gas. In particular, the protective film 116 coversthe sides, at which the layers between the PZT films 113, 114 and the Ptelectrodes 112, 115 terminate, to prevent the reducing gas frompenetrating into these layers.

It is to be noted that a structure without the protective film 116 asshown in FIG. 13B has also good electrical characteristics and if theprotective film 116 is provided, the electrical characteristics will befurther enhanced.

Referring to FIGS. 14A through 14C a process for manufacturing aferroelectric capacitor in this preferred embodiment will be describedin detail below. As shown in FIG. 14A, an adhesion film 111 having athickness of about 20 nm and a Pt electrode 112 having a thickness ofabout 200 nm are sequentially deposited on a substrate 110 bysputtering. Then, a first PZT film 113 is deposited on the Pt electrode112 by the sol-gel method or sputtering method. The thickness of thefirst PZT film 113 is in the range of from 5 nm to 50 nm, preferably inthe range of from 10 nm to 20 nm. AT this stage, the state of the firstPZT film 113 is an amorphous state.

Thereafter, a heat treatment is carried out at a temperature of 650° C.to 750° C. in an atmosphere of oxygen to crystallize the first PZT film113. At this crystallizing step, a diffusion reaction is caused betweenthe Pt electrode 112 and the first PZT film 113 to crystallize the firstPZT film 113 containing Pt. Thus, the first PZT film 113 becomesconductive.

Then, as shown in FIG. 14B, a second PZT film 114 is deposited on thefirst PZT film 113 by the sol-gel method or sputtering method. Thethickness of the second PZT film 114 is in the range of from 50 nm to300 nm. Then, a heat treatment is carried out at a temperature of 650°C. to 750° C. in an atmosphere of oxygen to crystallize the second PZTfilm 114. It has been confirmed that Pt is hardly diffused in the secondPZT film 114 at this crystallizing step. The reason for this is that Pt,which has been incorporated into the first PZT film 113, has a smalldegree of freedom since the first PZT film 113 has been crystallized atthis stage. In addition, the reason is that the diffusion of Pt from thebottom Pt electrode 112 into the second PZT film 114 is inhibited by thecrystallized first PZT film 113.

Thereafter, as shown in FIG. 14C, a top Pt electrode 115 is deposited onthe second PZT film 114 by sputtering. Although the subsequent steps arenot shown, the stacked structure obtained by the above described stepsis patterned to form a ferroelectric capacitor C1. Specifically, thepatterning step is carried out as follows. First, the top Pt electrode115, the second PZT film 114 and the first PZT film 113 are sequentiallyetched using a predetermined resist pattern. This etching is carried outby using the RIE method using Ar/C1 ₂/CF₄ gas and by carrying out anover etching so as to slightly remove the surface of the bottom Ptelectrode 112. Then, after the resist pattern is removed to form aprotective film 116, a resist pattern for covering a broader range thanthe removed resist pattern is formed again to etch the protective film116 and the bottom Pt electrode 112. The protective film 116 may beformed preferably at least one selected from the group consisting ofAl_(x)O_(y), TiO_(x), ZrO_(x), MgTiO_(x), Si_(x)N_(y), andTi_(x)Si_(y)N_(z), which are capable of blocking the penetration ofhydrogen or the like.

Furthermore, with respect to the memory cells of the ferroelectricmemory in this preferred embodiment, which have theone-transistor/one-capacitor structure comprising a ferroelectriccapacitor C1 and a MS transistor, an example of the memory structure isshown in FIG. 15. As shown in this figure, a MOS transistor 103 isformed on a silicon substrate 101 in a region defined by an elementisolating insulator film 102, and the top thereof is covered with aninterlayer insulator film 104 of a silicon oxide film or the like.

A contact plug 107 to one of the diffusion layers of the MOS transistor103 is embedded in the interlayer insulator film 104. A bit line 105connected to the other diffusion layer of the MOS transistor 103 is alsoembedded in the interlayer insulator film 104. On the interlayerinsulator film 104, the above described ferroelectric capacitor C1 isformed. In the shown example, a bottom Pt electrode 112 is connected tothe MOS transistor 103 via the contact plug 107, and the connection nodethereof serves as a memory node. Moreover, an interlayer insulator film117 is formed on the capacitor C1. On the interlayer insulator film 117,a plate interconnection 118 connected to the top Pt electrode 115 of thecapacitor C1 is formed.

FIG. 16 shows the polarization of the ferroelectric capacitor C1 in thispreferred embodiment, in comparison with the conventional ferroelectriccapacitor. This comparison is conducted for FRAM products for which thehydrogen treatment has been performed.

The conventional ferroelectric capacitor is produced by forming a singlePZT film on a bottom Pt electrode, crystallizing the PZT film by a heattreatment, and then, forming a top Pt electrode thereon. The spontaneouspolarization in the conventional ferroelectric capacitor was about2Pr1=20 μC/cm², whereas the spontaneous polarization in this preferredembodiment was about 2Pr2=30 μC/cm².

The reasons why the above described great spontaneous polarization canbe obtained in this preferred embodiment are that the PZT film has atwo-layer structure, and the PZT film 113 is crystallized before thesecond PZT film 114 is formed, so that Pt is diffused into the first PZTfilm 113 from the bottom Pt electrode 112, and that Pt is not diffusedin the second PZT film 114. This has been revealed by the results of theSIMS analysis.

FIGS. 17 and 18 show the distributions of Pt and Pb obtained by the SIMSanalysis, with respect to the ferroelectric capacitor C1 in thispreferred embodiment and the conventional ferroelectric capacitor. Inthe case of the conventional ferroelectric capacitor, it can be seenfrom FIG. 18 that a deep Pt diffusion layer extending from the bottom Ptelectrode exists in the PZT film. As described above, this Pt diffusionlayer is conductive, so that it is not possible to obtain a goodspontaneous polarization. On the other hand, in the case of thispreferred embodiment, it can be seen from FIG. 17 that Pt is hardlydiffused in the second PZT film 114 although Pt is diffused in the firstPZT film 113.

FIG. 19A shows the structure of the fourth preferred embodiment of aferroelectric capacitor C2 according to the present invention, which isapplied to a ferroelectric memory, so as to correspond to FIG. 13A. Asubstrate 110 is a silicon substrate covered with an insulator film of asilicon oxide film or the like. A Pt electrode 112 serving as a bottomelectrode is formed on the substrate 110 via an adhesion film 111. Theadhesion film 111 is provided for improving the adhesion of the Ptelectrode 112 to the silicon oxide film or the like. On the Pt electrode112, a first PZT film 113, a second PZT film 114 and a third PZT film121 are stacked. On the third PZT film 121, a Pt electrode 115 is formedas a top electrode.

In this preferred embodiment, the ferroelectric capacitor C2 ispatterned as shown in the figure, and covered with a protective film 116against a reducing gas. In particular, the protective film 116 coversthe sides, to which the layers between the PZT films 113, 114 and the Ptelectrodes 112, 115 are exposed, to prevent the reducing gas frompenetrating into these layers.

It is to be noted that as shown in FIG. 19B, a structure without theprotective film 116 has also good electrical characteristics and if theprotective film 116 is provided, the electrical characteristics will befurther enhanced.

FIGS. 20A through 20C show a process for manufacturing a ferroelectriccapacitor C2 in this preferred embodiment so as to correspond to FIGS.14A through 14C. As shown in FIG. 20A, an adhesion film 111 having athickness of about 20 nm and a Pt electrode 112 having a thickness ofabout 200 nm are sequentially deposited on a substrate 110 bysputtering. In this state, a heat treatment is preferably carried out atabout 500° C. in an atmosphere of oxygen. Then, a first PZT film 113 isdeposited on the Pt electrode 112 by the sol-gel method or sputteringmethod. The thickness of the first PZT film 113 is in the range of from5 nm to 50 nm, preferably in the range of from 10 nm to 20 nm. At thisstage, the state of the first PZT film 113 is an amorphous state.

Thereafter, a heat treatment is carried out at a temperature of 650° C.to 750° C. in an atmosphere of oxygen to crystallize the first PZT film113. At this crystallizing step, a diffusion reaction is caused betweenthe Pt electrode 112 and the first PZT film 113 to crystallize the firstPZT film 113 containing Pt.

Then, as shown in FIG. 20B, a second PZT film 114 is deposited on thefirst PZT film 113 by the sol-gel method or sputtering method. Thethickness of the second PZT film 114 is in the range of from 300 nm to2000 nm. Then, a heat treatment is carried out at a temperature of 650°C. to 750° C. in an atmosphere of oxygen to crystallize the second PZTfilm 114. At this crystallizing step, Pt is hardly diffused in thesecond PZT film 114.

Thereafter, as shown in FIG. 20C, a third PZT film 121 is deposited onthe second PZT film 114 by sol-gel method or sputtering method so as tohave a thickness of 5 nm to 50 nm, preferably 10 nm to 20 nm.Subsequently, a top Pt electrode 115 is deposited thereon. Thereafter, aheat treatment is carried out at a temperature of 650° C. to 750° C. inan atmosphere of oxygen to crystallize the third PZT film 121. At thiscrystallizing step, Pt is diffused in the third PZT film 121 from thetop Pt electrode 115, so that the third PZT film 121 becomes conductive.

Then, the stacked structure thus obtained is patterned to form aprotective film 116 similar to the above described first preferredembodiment.

In this fourth preferred embodiment unlike the third preferredembodiment, the PZT film has a three-layer structure, and the third PZTfilm 121 is crystallized after the top Pt electrode 115 is deposited. Bythis crystallization after forming the top Pt electrode 115, a lowresistance contact is obtained between the third PZT film 121 and thetop Pt electrode 115. Although Pt is diffused in the third PZT film 121as described above, the second PZT film 114 may be previouslycrystallized so that Pt is hardly diffused therein.

FIG. 21 shows the distributions of Pt and Pb obtained by the SIMSanalysis, with respect to the ferroelectric capacitor C2 in thispreferred embodiment. As shown in this figure, Pt is hardly diffused inthe second PZT film 114 although most Pt is diffused in the first andthird PZT film 113 and 121.

Therefore, also in the fourth preferred embodiment, the second PZT film114 serves as a substantial capacitor dielectric film for determiningthe spontaneous polarization, and has a small leak and an excellentspontaneous polarization. In addition, the thickness of theferroelectric capacitor can be decreased by selecting the thickness ofthe second PZT film 114. Moreover, in the second preferred embodiment,the first PZT film 113 serves as a metallic layer for inhibiting thehydrogen degradation of the second PZT film 114 due to the catalysis ofthe bottom Pt electrode 112. Thus, it is possible to realize a stablespontaneous polarization which has smaller degradation.

The present invention may be applied to a DRAM or the like using ahigh-dielectric capacitor, not only to the ferroelectric capacitor. Inthis case, for example, BSTO, i.e., (Ba, Sr)TiO₃, having a relativedielectric constant of 50 or more is used as a metal oxide dielectric ofa high-dielectric capacitor. The preferred embodiments of the presentinvention applied to a high-dielectric capacitor will be describedbelow.

FIG. 22 shows the structure of the fifth preferred embodiment of ahigh-dielectric capacitor C11 according to the present invention so asto correspond to the third preferred embodiment shown in FIG. 13B. Afirst BSTO film 122 and a second BSTO film 123 are stacked on a bottomPt electrode 112, and a top Pt electrode 115 is formed thereon. Themanufacturing process is the same as that in the third preferredembodiment (FIGS. 14A-14C). At a heat treatment step for crystallizingthe first BSTO film 122, Pt is diffused in the first BSTO film 122. Thesecond BSTO film 123 formed thereafter is crystallized before the top Ptelectrode 115 is deposited, so that Pt is hardly diffused in the secondBSTO film 123.

In the case of this preferred embodiment, there is originally no problemin that the spontaneous polarization is degraded by the reducing powerof hydrogen or the like. However, since the second BSTO film 123 servesas the capacitor dielectric film of a substantial high-dielectriccapacitor having a small leak, it is possible to obtain excellentelectrical property. In addition, since the element constituting thebottom electrode is not diffused into the second BSTO film 123, there isan advantage in that the scaling of the thickness of the film can beeasily carried out.

FIG. 23 shows the structure of the sixth preferred embodiment of ahigh-dielectric capacitor C12 according to the present invention so asto correspond to the fourth preferred embodiment shown in FIG. 19B. Afirst BSTO film 122, a second BSTO film 123 and a third BSTO film 124are stacked on a bottom Pt electrode 112 and a top Pt electrode 115 isformed thereon. The manufacturing process is the same as that in thefourth preferred embodiment (FIGS. 20A-20C). At a heat treatment stepfor crystallizing the first BSTO film 122, Pt is diffused in the firstBSTO film 122. In addition, Pt is diffused in the third BSTO film 124 bycrystallization after the top Pt electrode 115 is deposited. In thesecond BSTO film, Pt is hardly diffused.

By employing such a structure, the reduction of the BSTO by hydrogen iseffectively prevented, because the metallized layer 124. Also in thispreferred embodiment, it is possible to easily carry out the scaling ofthe thickness of the film.

The first metal oxide dielectric films in each of the above describedpreferred embodiments may comprise a plurality of layers formed by aplurality of steps. Specifically, the steps of depositing a thin metaloxide dielectric film, carrying out a heat treatment forcrystallization, and depositing the next metal oxide dielectric film arerepeated.

By such a technique, the total thickness of the first metal oxidedielectric film can be decreased. Because the depth of the Pt diffusioninto the top metal oxide dielectric film from the bottom Pt electrodecan be smaller than that of a first metal oxide dielectric film formedof a single layer, by overlapping thin metal oxide dielectric filmswhile sequentially crystallizing the films.

The present invention should not be limited to the above describedpreferred embodiments. For example, while the PZT has been used as themetal oxide ferroelectric film of the ferroelectric capacitor in theabove described preferred embodiments, other ferroelectric films, e.g.,SBT (SrBi₂Ta₂O₉), may be used. The high-dielectric capacitor may alsouse other metal oxide dielectric films having a relative dielectricconstant of 50 or more.

Moreover, the top and bottom electrodes should not be limited to Ptelectrodes, but the top and bottom electrodes may be formed of Ru, RuO₂,SrRuO₃, Ir and their oxides or the like.

As described above, according to the present invention, the metal oxidedielectric film has a plurality of layers, so that it is possible toobtain a semiconductor integrated circuit having a capacitor, which hasa small leak, which can easily carry out the thickness of the film andwhich has excellent charge holding characteristics.

FIG. 24 shows a sectional structure of a seventh preferred embodiment ofa ferroelectric capacitor 220 formed on a silicon substrate 210 coveredwith an insulator film, according to the present invention. The top Ptelectrode 215 and PZT film 214 of the ferroelectric capacitor 220 aresequentially patterned, and the bottom Pt electrode 212 thereof ispatterned so as to have a portion 212 b extending to the outside of thePZT film 214. In this preferred embodiment, an adhesion film 211 forimproving the adhesion of the bottom Pt electrode 212 to an oxide filmis formed below the bottom Pt electrode 212.

In this preferred embodiment, the surface of the portion 212 b extendingto the outside of the PZT film 214 of the bottom Pt electrode 212 isover-etched at an etching step, so that the level of the surface islower than that of the layer 213 between the PZT film 214 and the bottomPt electrode 212 by d. In addition, a protective film 216 againsthydrogen gas and a halogen gas is formed so as to cover a rangeextending from the extending portion 212 b of the bottom Pt electrode212 to the surface of the top Pt electrode 215 via the sides of the PZTfilm 214 and top Pt electrode 215.

The ferroelectric capacitor 220 is covered with a passivation film (oran interlayer insulator film) 217 of an insulator film, such as asilicon oxide film, and a contact hole is formed in the passivation film217 so that a metal interconnection 218 is connected to theferroelectric capacitor 220. The bottom Pt electrode 212 also contactsan interconnection (not shown) or a terminal layer (not shown) of a MOStransistor (not shown) at an appropriate position.

FIGS. 25A through 25D are sectional views showing a process formanufacturing a ferroelectric capacitor 220 in this preferredembodiment. As shown in FIG. 25A, an adhesion film 211 having athickness of 20 nm and a Pt film 212 having a thickness of 150 nmserving as a material of a bottom electrode are sequentially depositedon a substrate 210 by sputtering. Subsequently, a PZT film 214 isdeposited as a ferroelectric film by the sol-gel method or sputteringmethod so as to have a thickness of 200 nm. After the PZT film 214 isdeposited, a heat treatment is carried out at 750° C. in an atmosphereof oxygen to crystallize the PZT film 214. Moreover, a Pt film 215having a thickness of 100 nm serving as a material of a top electrode isdeposited on the PZT film 214 by sputtering. The materials used for theadhesion film are Al, Ti, Zr, Mg, MgTi and their oxides.

Then, as shown in FIG. 25B, a resist pattern 221 is formed by alithography process, and the Pt film 215 and the PZT film 214 aresequentially etched using the resist pattern 221 as an etching resistantmask. To the sequential etching of the Pt film 215 and PZT film 214, theRIE method using Ar/Cl₂/CF₄ gas is applied. At this time, the supply gasis switched so that Cl₂ is mainly supplied during etching of the Pt film215 and CF₄ is mainly supplied during etching of the PZT film 214.

At this etching step, as shown in FIG. 25B, the Pt film 212 exposed tothe outside of the patterned top Pt electrode 215 and PZT film 214 isover-etched so that the level of the surface of the Pt film 212 is lowerthan that of the layer 213 between the PZT film 214 and the Pt film 212by d. According to experiments, the thickness of the surface portionremoved from the Pt film 212, i.e., the over-etched amount d, ispreferably 0.5% or more of the thickness of the Pt film 212, morepreferably 1% or more thereof, so that it is possible to inhibit thepenetration of a halogen gas when the Pt film 212 is further etched andto inhibit the penetration of hydrogen after the passivation film isformed. The over-etched amount d is preferably 50% or less of thethickness of the Pt film 212 in order to prevent increase of electricalresistance.

Subsequently, after the resist pattern 221 is removed, a protective film216 is formed so as to cover the surface of the bottom Pt film 212, thesides of the PZT film 214 and top Pt electrode 215, and the surface ofthe top Pt electrode. The protective film 216 is preferably an insulatorfilm having a specific resistance of 100 kΩ·cm or more.

Specifically, the protective film 216 is made of material selected fromthe group consisting of Al_(x)O_(y), TiO_(x), ZrO_(x), MgO_(x), andMgTiO_(x). When these materials are used, the thickness of theprotective film 216 is in the range of from 2 nm to 300 nm. When thethickness is less than 2 nm, it is not possible to effectively inhibitthe penetration of the reducing element. When the thickness exceeds 300nm, the working time is too long, and the thickness of the wholecapacitor is too large, so that it is not suitable for multilayering.

Thereafter, as shown in FIG. 25D, a resist pattern 222 for covering alarger area than the resist pattern 221 is formed. Then, the protectivefilm 216, and the Pt film 212 and Ti film 211 underlying the protectivefilm 216 are sequentially etched, and the Pt film 212 is patterned so asto have a predetermined range of portion 212 b extending to the outsideof the PZT film 214. Thereafter, the resist pattern 222 is removed, anda passivation film 217 is deposited as shown in FIG. 24. Then, a contacthole is formed, and a metal interconnection 218 is formed. After thecontact hole is formed, a recovery heat treatment is preferably carriedout at a temperature of about 650° C. in an atmosphere of oxygen. Themetal interconnection 218 is, e.g., a TiN/Al stacked film.

According to this preferred embodiment, at the etching step of FIG. 25D,the level of the surface of the extending portion 212 b of the bottom Ptelectrode 212 is lower than the level of the layer 213 between the PZTfilm 214 and the bottom Pt electrode 212. Thus, it is possible toprevent the etching gas, such as C1 or F, from penetrating into thelayer 213 from the etched end surface. Therefore, the layer 213 is notdamaged. For the same reason, even if hydrogen annealing is carried outin the state of FIG. 24 wherein the protective film 216 and thepassivation film 217 are formed, it is possible to inhibit hydrogen frompenetrating into the layer 213 via the passivation film 217.

Thus, according to this preferred embodiment, it is possible to obtain areliable ferroelectric capacitor which is able to prevent the decreaseof remnant polarization and the peeling of films.

The Q-V characteristics of the conventional structure shown in FIG. 1Aand the ferroelectric capacitor in this preferred embodiment are shownin FIG. 16.

In addition, an example of the detailed structure of the substrate 210in this preferred embodiment is shown in FIG. 15.

FIG. 26 is a sectional view showing the structure of an eighth preferredembodiment of a ferroelectric capacitor according to the presentinvention, and FIGS. 27A through 27E are sectional views showing amanufacturing process in this preferred embodiment. The same referencenumbers are applied to parts corresponding to those in the precedingpreferred embodiments, and the detailed descriptions thereof areomitted. The protective film 216 can be omitted as shown in FIGS. 13Band 19B.

As shown in FIG. 27A, required films are sequentially deposited similarto the preceding preferred embodiments. Thereafter, as shown In FIG.27B, a top Pt film 215 is etched using a resist pattern 221, andsubsequently, a PZT film 214 is etched. At this time, as shown in thefigure, the etching of the PZT film 214 is stopped on the way. Then, theresist pattern 221 is removed, and a resist pattern 221 b having aslightly larger area than that of the resist pattern 221 is newly formedto etch the rest of the PZT film 214 as shown in FIG. 27C. Similar tothe preceding preferred embodiments, a part of the surface of the bottomPt film 212 is sequentially etched at the step of patterning the PZTfilm 214.

Thereafter, similar to the preceding preferred embodiments, a protectivefilm 216 is deposited (FIG. 27D), and a resist pattern 222 is formed tosequentially etch the protective film 216 and the bottom Pt film 212(FIG. 27E).

According to this preferred embodiment, in addition to the advantagesobtained by the preceding preferred embodiments, the followingadvantages are obtained. That is, at the step of patterning the PZT film214 shown In FIG. 27C, the layer between the top Pt electrode 215 andthe PZT film 214 is protected by the resist pattern 221 b. Thus, even ifthe Pt film is adhered to the side of the PZT film 214 when the bottomPt film 212 is over-etched, the layer between the top Pt electrode 215and the PZT film 214 is protected, so that it is possible to surelyprevent the short-circuit between the top and bottom electrodes.

As described above, according to the present invention, it is possibleto provide a semiconductor device having a ferroelectric capacitor,which can effectively inhibit the reducing element from causing thedamage to the layer between the ferroelectric film and the bottomelectrode and from peeling the films to reduce the degradation inremnant polarization.

FIGS. 28A through 28D show a process for manufacturing a ninth preferredembodiment of a ferroelectric capacitor of a FRAM according to thepresent invention. In this preferred embodiment, a hydrogen barrier filmis provided in an interlayer insulator film covering a ferroelectriccapacitor so as to surround the ferroelectric capacitor. As shown inFIG. 28A, after a transistor (not shown) is formed on a siliconsubstrate 301, the surface thereof is covered with an interlayerinsulator film 302 of a silicon oxide film or the like to be flattened.A ferroelectric capacitor C comprising a bottom Pt electrode 303, a PZTfilm 304 and a top Pt electrode 305 is formed on the interlayerinsulator film 302 via an adhesion layer 401.

Specifically, the bottom Pt electrode 303 having a thickness of about100 nm is deposited by sputtering, and the PZT film 304 having athickness of about 150 nm is deposited thereon by a sputtering method orsol-gel method to be crystallized by the rapid thermal anneal (RTA)method at 650° C. in an atmosphere of oxygen. On the PZT film 304, thetop Pt electrode film having a thickness of about 50 nm is deposited.Then, these stacked films are sequentially etched to form theferroelectric capacitor C. At this time, the top Pt electrode 305 isetched using a first mask material (not shown), and the PZT film 304 andthe bottom Pt electrode film 303 are etched using a second mask materialhaving a larger area than that of the first mask material.

The ferroelectric capacitor C thus formed is covered by a thininterlayer insulator film 306 a is deposited as shown in FIG. 28B. Then,as shown in FIG. 28C, a hydrogen barrier film 402 is deposited on theinterlayer insulator film 306 a, and an interlayer insulator film 306 bis deposited thereon. That is, the interlayer insulator films 306 a and306 b are formed so that the hydrogen barrier film 402 is providedbetween the interlayer insulator films 306 a and 306 b.

Furthermore, in this preferred embodiment, the thickness of theinterlayer insulator film 306 a is 0.2 times or more and twice or lessas large as the thickness of the top Pt electrode 305, the PZT film 304and the bottom Pt electrode 303, or 0.05 times or more and three timesor less as large as the thickness of the ferroelectric capacitor C, sothat it Is possible to deposit a good coverage of the hydrogen barrierfilm 402. Finally, as shown in FIG. 28D, a contact hole is formed, and aterminal interconnection 307 connected to the top Pt electrode 305 isformed.

The hydrogen barrier film 402 runs from the contact 307 to the side ofthe bottom electrode 303 as shown by the solid line. However, thehydrogen barrier film 402 may extend to further area, for example, anext element area, as shown by the broken line. This expression isapplicable to following various embodiments.

Also in this preferred embodiment, the hydrogen barrier film 402 is afilm having a hydrogen diffusion coefficient of 1E-5 cm²/s or less,preferably a metal oxide film having a specific resistance of 1 kΩ-cm ormore, typically an aluminum oxide (Al₂O₃) film. When the hydrogenbarrier film is thus inserted into the interlayer insulator film, it ispossible to prevent the degradation in the performance of theferroelectric capacitor. In addition, the hydrogen barrier film providedin the interlayer insulator film can inhibit the damage to theferroelectric capacitor at the step of depositing the passivation film(usually an SiN film) for covering the top surface of the element.Moreover, the interlayer insulator film 306 a serves to prevent areaction from being caused by directly contacting the hydrogen barrierfilm with the ferroelectric capacitor C. In addition, since the Al₂O₃film is an insulator film, the Al₂O₃ film can be inserted into theinterlayer insulator film over the whole surface without the need ofpatterning, and the short-circuit of the contact to the diffusion layeris not caused. Moreover, the hydrogen barrier film is formed via theinterlayer insulator film, so that it is possible to decrease the stressof the hydrogen barrier film.

FIG. 28E shows a structure where a silicon nitride (SiN) film 410 isdeposited on the hydrogen barrier film 402.

In this preferred embodiment, the hydrogen barrier film is preferably atleast one selected from the group consisting of Al_(x)O_(y), TiO_(x),ZrO_(x), MgO_(x) and MgTiO_(x), in addition to Al₂O₃.

FIG. 29A Is a sectional view of the tenth preferred embodiment of aferroelectric capacitor according to the present invention, whereininterlayer insulator films 306 c and 306 d are stacked on the structurein the above described ninth preferred embodiment, and a hydrogenbarrier film 403 is provided between the interlayer insulator films 306c and 306 d under a passivation film 308 of an SiN film. When aplurality of hydrogen barrier films are thus provided between theinterlayer insulator films, it can be expected to more surely preventthe hydrogen diffusion. In addition, it has been confirmed that thisstructure can effectively reduce the damage due to the deposition of thepassivation film of SiN.

FIG. 29B shows a structure which is based on the structure of FIG. 29Aand wherein an interlayer insulator film 306 b is flattened and aninterconnection 307 is formed thereon.

FIG. 29C shows a structure wherein the interlayer insulator film 306 aof FIG. 29B is flattened and a hydrogen barrier 402 is formed thereon.

FIG. 29D shows a structure wherein a silicon nitride film 410 isdeposited on the hydrogen barrier film 402 In FIG. 29B to enhancebarrier performance.

FIG. 30A shows an eleventh preferred embodiment obtained by modifyingthe structure in the ninth preferred embodiment. That is, in thispreferred embodiment, the level of the bottom of a hydrogen barrier film402 provided between interlayer insulator films 306 a and 306 b is lowerthan the level of the bottom of a bottom Pt electrode 303 of aferroelectric capacitor C by Δt. In such a structure, it is possible tonarrow the diffusion path of hydrogen gas supplied to the region of theferroelectric capacitor C via the interlayer insulator film below thehydrogen barrier film 402, so that it is possible to more effectivelyprevent the hydrogen diffusion. Moreover, it is possible to obtain thesame advantages as those in the tenth preferred embodiment.

FIG. 30B shows a structure which is based on the structure of FIG. 30Aand wherein a hydrogen barrier film 402 is patterned in a predeterminedrange covering the region of a ferroelectric capacitor C. Since it ispossible to more effectively prevent the hydrogen diffusion by arrangingthe hydrogen barrier film 402 below the bottom of a bottom Pt electrode303 around the capacitor, it can be expected to sufficiently prevent thediffusion of hydrogen even if the hydrogen barrier 402 is thus partiallyinserted in the interlayer insulator film, not in the whole surface ofthe interlayer insulator film. In addition, in FIG. 30B, the interlayerinsulator film 306 b is flattened.

FIGS. 31A through 31G show a process for manufacturing a twelfthpreferred embodiment of a ferroelectric capacitor of a FRAM according tothe present invention. In this preferred embodiment, the capacitor hasdouble insulation films on the top electrode.

As shown in FIG. 31A, on an insulating base layer (not shown), a thinconductive Pt layer 410 for a bottom electrode, a PZT film 412 as aferroelectric thin film, and a thin conductive Pt layer 414 for a topelectrode are successively formed by e.g. sputtering method. Then anoxide film 416 (thin film for a first insulating film) is deposited onthe top electrode film 414 for a thickness of 3000 Angstrom using aplasma CVD method. Then a photoresist is coated on the oxide film 416and is subjected to patterning to obtain a photoresist mask 418 forforming the top electrode.

Next, as shown in FIG. 31B, the oxide film 416 is etched using forexample RIE (Reactive Ion Etching) to obtain an oxide film mask (firstinsulating film) 416A. After the etching, the photoresist mask 418 isremoved by ashing.

Next, as shown in FIG. 3 IC, the film for top electrode 414 isdry-etched using the oxide film mask 416A and RIE method. At thisetching, slight residual 420 may remain at the side wall of the oxidefilm mask 416A.

Then as shown in FIG. 31D, an oxide film (second insulating film) 422 of3000 Angstrom thick is deposited on the top electrode 414A and on theferroelectric thin film 412 using the plasma electrical method. Then aphotoresist is applied and patterned, a photoresist mask for forming aphotoresist mask 424 for forming the ferroelectric film.

Next, as shown in FIG. 31E, etching the oxide film 422 using thephotoresist mask 424 forms an oxide mask (second insulating film) 422A.At this etching, PZT residual 426 may be generated. However, this can berelatively easily removed by hydrochloric acid treatment.

Next, as shown in FIG. 31F, the ferroelectric film 412 is etched by RIEusing the photoresist mask 424 to form a patterned ferroelectric film412A. At this etching, residuals 428 of Pt and PZT tend to be formed.Since the PZT residual of the residual 428 can be relatively easilyremoved by the hydrochloric acid treatment, the PZT residual is removed.The Pt residual will be removed in the next step for etching the bottomelectrode film 410.

Next, as shown in FIG. 31G, the photoresist mask 424 is removed byashing. Then the film 410 for bottom electrode is dry-etched by RIEusing the oxide mask 422A to obtain the bottom electrode 410A. At thistime, a residual 429 of Pt may be generated. However, the residual 420from the top electrode 414A and the residual 429 from the bottomelectrode 410A are isolated by oxide masks 416A and 422A and they arenot short-circuited.

In this step, though the PZT film and the Pt film are patterned usingthe oxide mask, the photoresist which has not been removed by ashing canbe used to pattern the PZT and Pt films.

In this embodiment, since two insulating films exist on the topelectrode, barrier effect for the top electrode is enhanced.

Furthermore, since the insulating film used as a mask for forming thetop electrode is remained, the residual generated during forming thebottom electrode will not be in contact with the top electrode, whichwill improve yield and reliability of FRAM.

In this embodiment, as shown in 31G, residuals 420 and 429 are remained.However, as shown in 31H, these residuals can be thoroughly removed toimprove reliability.

FIG. 32 is a sectional view showing an embodiment which is a combinationof structures of FIG. 26 and FIG. 11. In this embodiment, the capacitorhas a stepwise configuration and stack of two layers of PZT and twotitanium films.

FIG. 33 is a sectional view showing an embodiment which is a combinationof structures of FIG. 26 and FIG. 13. In this embodiment, In thisembodiment, the capacitor has a stepwise configuration and stack of twolayers of PZT.

FIG. 34 is a sectional view showing an embodiment which is a combinationof structures of FIG. 26 and FIG. 19. In this embodiment, the capacitorhas a stepwise configuration and stack of three layers of PZT.

FIG. 35 is a sectional view showing an embodiment which is a combinationof structures of FIG. 26 and FIG. 23. In this embodiment, the capacitorhas a stepwise configuration and stack of three layers of BSTO.

FIG. 36 is a sectional view showing an embodiment which is a combinationof structures of FIG. 28D and FIG. 11. In this embodiment, the capacitorhas a stepwise configuration with smaller area as going upper layers andstack of two layers of PZT and two titanium films.

FIG. 37 is a sectional view showing an embodiment which is a combinationof structures of FIG. 28D and FIG. 13. In this embodiment, the capacitorhas a stepwise configuration with smaller area as going upper layers andstack of two layers of PZT.

FIG. 38 is a sectional view showing an embodiment which is a combinationof structures of FIG. 28D and FIG. 19. In this embodiment, the capacitorhas a stepwise configuration with smaller area as going upper layers andstack of three layers of PZT.

FIG. 39 is a sectional view showing an embodiment which is a combinationof structures of FIG. 28D and FIG. 23. In this embodiment, the capacitorhas a stepwise configuration with smaller area as going upper layers andstack of three layers of BSTO.

FIG. 40 is a sectional view showing an embodiment which is a combinationof structures of FIG. 29A and FIG. 11. In this embodiment, the capacitorhas a double barrier structure and stack of two layers of PZT, and twotitanium films.

FIG. 41 is a sectional view showing an embodiment which is a combinationof structures of FIG. 29A and FIG. 13. In this embodiment, the capacitorhas a double barrier structure and stack of two layers of PZT.

FIG. 42 is a sectional view showing an embodiment which is a combinationof structures of FIG. 29A and FIG. 19. In this embodiment, the capacitorhas a double barrier structure and stack of three layers of PZT.

FIG. 43 is a sectional view showing an embodiment which is a combinationof structures of FIG. 29A and FIG. 23. In this embodiment, the capacitorhas a double barrier structure and stack of three layers of BSTO.

FIG. 44 is a sectional view showing an embodiment which is a combinationof structures of FIG. 30A and FIG. 11. In this embodiment, the capacitorhas a stepwise configuration and a barrier with its extending portionsbeing lower than the stack structure of two layers of PZT and twotitanium films.

FIG. 45 is a sectional view showing an embodiment which is a combinationof structures of FIG. 30A and FIG. 13. In this embodiment, the capacitorhas a stepwise configuration and a barrier with its extending portionsbeing lower than the stack structure of two layers of PZT.

FIG. 46 is a sectional view showing an embodiment which is a combinationof structures of FIG. 30A and FIG. 19. In this embodiment, the capacitorhas a stepwise configuration and a barrier with its extending portionsbeing lower than the stack structure of three layers of PZT.

FIG. 47 is a sectional view showing an embodiment which is a combinationof structures of FIG. 20A and FIG. 23. In this embodiment, the capacitorhas a stepwise configuration and a barrier with its extending portionsbeing lower than the stack structure of three layers of BSTO.

FIG. 48 is a sectional view showing an embodiment which is a combinationof structures of FIG. 29A and FIG. 31G. In this embodiment, since thecapacitor has double insulation films 416A and 422A, residual fences 420and 429 will not cause a short-circuit.

FIG. 49 is a sectional view showing an embodiment which is a combinationof structures of FIG. 29A and FIG. 31H. In this embodiment, residualfences are thoroughly removed, which will decrease the possibility ofshort-circuit.

FIG. 50 is a sectional view showing an embodiment which is a variationof the combination of structures of FIG. 29A and FIG. 31G. Thisembodiment is similar to the embodiment of FIG. 48, but the hydrogenbarrier film extends to the level lower than the bottom electrode.

FIG. 51 is a sectional view showing an embodiment which is a variationof the combination of structures of FIG. 29A and FIG. 31H. Thisembodiment is similar to the embodiment of FIG. 49, but the hydrogenbarrier film extends to the level lower than the bottom electrode.

FIG. 52 is a sectional view showing an embodiment in which an interlayerinsulator material containing metal oxide is used. Material used here ispreferably at least one selected from the group consisting ofAl_(x)O_(y), TiO_(x), ZrO_(x), MgO_(x), PbO_(x), BiO_(x) and MgTiO_(x).

When such an interlayer insulator is employed, the metal oxide functionsas a hydrogen barrier. Accordingly, good behavior is attained withoutusing the hydrogen barrier film.

While the present invention has been disclosed in terms of the preferredembodiment in order to facilitate better understanding thereof, itshould be appreciated that the invention can be embodied in various wayswithout departing from the principle of the invention and that theinvention should be understood to include all possible embodiments anmodification to the shown embodiments.

Therefore, the present invention should not be limited to the abovedescribed preferred embodiments. For example, the protective film may beformed of an insulator film at least one selected from the groupconsisting of Al_(x)O_(y), TiO_(x), ZrO_(x), MgO_(x) and MgTiO_(x). Inaddition, the ferroelectric film may be formed of SBT (SrBi₂Ta₂O₉) otherthan the PZT.

1. A semiconductor memory device comprising: a semiconductor substrate;an insulator film formed on said substrate; a ferroelectric capacitorhaving a bottom electrode, a ferroelectric film and a top electrode,which are sequentially stacked on said insulator film, saidferroelectric film being patterned on said bottom electrode having apredetermined pattern so as to have an area smaller than an area of saidbottom electrode; an interlayer insulation layer covering theferroelectric capacitor; and a hydrogen barrier film deposited on theinterlayer insulation layer so that at least a top and side of saidferroelectric capacitor are enveloped via said interlayer insulationlayer, wherein an extending portion of said hydrogen barrier film is ata level lower than said insulator film by a predetermined amount.
 2. Asemiconductor memory device comprising: a semiconductor substrate; afirst insulator film formed on said substrate; a ferroelectric capacitorhaving a bottom electrode, a ferroelectric film and a top electrode,which are sequentially stacked on said first insulator film, saidferroelectric film being patterned on said bottom electrode having apredetermined pattern so as to have an area smaller than an area of saidbottom electrode; a first interlayer insulation layer covering theferroelectric capacitor; a first hydrogen barrier film deposited on thefirst interlayer insulation layer so that at least a top and side ofsaid ferroelectric capacitor are enveloped via said first interlayerinsulation layer; a second interlayer insulation layer covering saidfirst hydrogen barrier film; and a second hydrogen barrier filmdeposited on said second interlayer insulation layer, wherein said firstand second hydrogen barrier films are disposed in a parallel plane.
 3. Asemiconductor memory device comprising: a semiconductor substrate; aninsulator film formed on said substrate; a ferroelectric capacitorhaving a bottom electrode, a ferroelectric film and a top electrode,which are sequentially stacked on said insulator film, saidferroelectric film being patterned on said bottom electrode having apredetermined pattern so as to have an area smaller than an area of saidbottom electrode; an interlayer insulation layer covering theferroelectric capacitor; a hydrogen barrier film deposited on theinterlayer insulation layer so that at least a top and side of saidferroelectric capacitor are enveloped via said interlayer insulationlayer; and a protective film formed on said hydrogen barrier film forprotecting against at least one of hydrogen gas and a halogen gas suchthat a surface of said top electrode and sides of said ferroelectricfilm and said bottom electrode are covered.
 4. The semiconductor memorydevice as set forth in claim 3, wherein a surface of said top electrodeand sides of said ferroelectric film and said bottom electrode arecovered with a protective film for protecting against at least one ofhydrogen gas and a halogen gas.
 5. A semiconductor device comprising: asemiconductor substrate; an insulator film formed on said substrate; aferroelectric capacitor having a bottom electrode, a ferroelectric filmand a top electrode, which are sequentially stacked on said insulatorfilm, said ferroelectric film being patterned on said bottom electrodehaving a predetermined pattern so as to have an area smaller than anarea of said bottom electrode; and an interlayer insulation layercovering the ferroelectric capacitor, said interlayer insulation layercontaining metal oxide material exhibiting hydrogen barriercharacteristics.